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Pull requests: llvm/circt

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Pull requests list

[HW] HWVectorization Part 3: Structural Patterns
#9749 opened Feb 24, 2026 by mafeguimaraes Loading…
[Arc] Add time operations for LLHD simulation support Arc Involving the `arc` dialect LLHD
#9747 opened Feb 24, 2026 by fabianschuiki Loading…
2
Migrated to PyConcrete* base classes
#9745 opened Feb 24, 2026 by jpienaar • Draft
[Datapath] Bug Fix for Sign-Extension Logic when Lowering Partial Products to Booth Arrays (#9726)
#9744 opened Feb 24, 2026 by cowardsa Loading…
2
[FIRRTL] Add CheckInstanceChoice pass to reject nested instance choices
#9743 opened Feb 24, 2026 by uenoku Loading…
2
[FIRRTL][LowerToHW] Add InstanceChoiceOp lowering, Part 1
#9742 opened Feb 24, 2026 by uenoku Loading…
Bump LLVM to 055b1efc1fe34106a8dc00a667708d5619077206.
#9741 opened Feb 23, 2026 by mikeurbach Loading…
1
fix: handle null cases for global memref
#9738 opened Feb 23, 2026 by Abhilekhgautam Loading…
1
[FIRRTL][InferResets] Only create reset ports for modules that need them
#9736 opened Feb 23, 2026 by seldridge • Draft
[HWToLLVM] Take the correct data layout alignment for alloca
#9734 opened Feb 23, 2026 by pscabot Loading…
6
[HW] Make sure the index type for arrays is at least i1
#9733 opened Feb 23, 2026 by pscabot Loading…
7
[RTGTest] Remove RV instructions RTG Involving the `rtg` dialect
#9732 opened Feb 23, 2026 by maerhart Loading…
1
[circt-bmc] Add multi-clock BMC support
#9729 opened Feb 22, 2026 by robert-at-pretension-io Loading…
3
[ImportVerilog][MooreToCore][Sim] Support queue element/range extractions in ImportVerilog Sim
#9727 opened Feb 22, 2026 by Lauriethefish Loading…
9
[circt-bmc] Lower LTL delay/clock patterns for BMC
#9722 opened Feb 22, 2026 by robert-at-pretension-io Loading…
3
[ImportVerilog] Support $ literal within queue indexing expressions ImportVerilog
#9719 opened Feb 21, 2026 by Lauriethefish Loading…
7
[ImportVerilog] Make sampled value functions' results usable by Moore ops ImportVerilog
#9718 opened Feb 21, 2026 by Arya-Golkari Loading…
1
[Synth] Add resource usage analysis
#9717 opened Feb 21, 2026 by uenoku Loading…
14
[FIRRTL] Check duplicate module port names in verifiers
#9716 opened Feb 21, 2026 by rhanqtl Loading…
1
2
[FIRRTL] Add conservative IMDCE handling for InstanceChoiceOp
#9710 opened Feb 20, 2026 by uenoku Loading…
[RTG] Add folders for most set operations
#9705 opened Feb 19, 2026 by maerhart • Draft
[FIRRTL] Support FInstanceLike operations in ModuleInliner
#9688 opened Feb 18, 2026 by uenoku Loading…
4
[Moore][ImportVerilog] Add support for fork-join blocks
#9682 opened Feb 17, 2026 by tdps2 Loading…
2
[ImportVerilog] Add dynamic array creation + 'size' and 'length' instructions to the moore dialect
#9679 opened Feb 16, 2026 by yuriyKulinchenko Loading…
4
[FIRRTL] Support merging layers in LinkCircuits
#9677 opened Feb 14, 2026 by unlsycn Loading…
10
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